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Date Sujet  Auteur
25.09.
* FPGA sensitivities
25.09.
+* Re: FPGA sensitivities
25.09.
|`- Re: FPGA sensitivities
25.09.
`- Re: FPGA sensitivities
25.09.
* Active HDL Entity Retention
27.09.
`* Re: Active HDL Entity Retention
27.09.
 `* Re: Active HDL Entity Retention
28.09.
  `* Re: Active HDL Entity Retention
28.09.
   `- Re: Active HDL Entity Retention
24.09.
* Multi-FPGA Interconnection: latest techniques
24.09.
`* Re: Multi-FPGA Interconnection: latest techniques
24.09.
 `* Re: Multi-FPGA Interconnection: latest techniques
24.09.
  `* Re: Multi-FPGA Interconnection: latest techniques
25.09.
   `* Re: Multi-FPGA Interconnection: latest techniques
25.09.
    `* Re: Multi-FPGA Interconnection: latest techniques
26.09.
     +* Re: Multi-FPGA Interconnection: latest techniques
28.09.
     |`* Re: Multi-FPGA Interconnection: latest techniques
30.09.
     | `- Re: Multi-FPGA Interconnection: latest techniques
26.09.
     `- Re: Multi-FPGA Interconnection: latest techniques
22.09.
* Is there any way to get a different font for code sections?
22.09.
`- Re: Is there any way to get a different font for code sections?
21.09.
* How powerful is Verilog at using parameters to specify designs?
22.09.
+* Re: How powerful is Verilog at using parameters to specify designs?
22.09.
|`* Re: How powerful is Verilog at using parameters to specify designs?
22.09.
| `* Re: How powerful is Verilog at using parameters to specify designs?
23.09.
|  `* Re: How powerful is Verilog at using parameters to specify designs?
23.09.
|   `* Re: How powerful is Verilog at using parameters to specify designs?
23.09.
|    +- Re: How powerful is Verilog at using parameters to specify designs?
23.09.
|    +* Re: How powerful is Verilog at using parameters to specify designs?
24.09.
|    |+* Re: How powerful is Verilog at using parameters to specify designs?
24.09.
|    ||`* Re: How powerful is Verilog at using parameters to specify designs?
25.09.
|    || +- Re: How powerful is Verilog at using parameters to specify designs?
25.09.
|    || +* Re: How powerful is Verilog at using parameters to specify designs?
25.09.
|    || |`* Re: How powerful is Verilog at using parameters to specify designs?
28.09.
|    || | `- Re: How powerful is Verilog at using parameters to specify designs?
25.09.
|    || `- Re: How powerful is Verilog at using parameters to specify designs?
23.09.
|    |`- Re: How powerful is Verilog at using parameters to specify designs?
23.09.
|    `- Re: How powerful is Verilog at using parameters to specify designs?
21.09.
`* Re: How powerful is Verilog at using parameters to specify designs?
22.09.
 `* Re: How powerful is Verilog at using parameters to specify designs?
23.09.
  `* Re: How powerful is Verilog at using parameters to specify designs?
23.09.
   +- Re: How powerful is Verilog at using parameters to specify designs?
23.09.
   `- Re: How powerful is Verilog at using parameters to specify designs?
21.09.
o Exponential Regression by XSG
20.09.
* exponential regression in XSG
20.09.
`- Re: exponential regression in XSG
16.09.
* Is it illegal to use an (enum) as a Verilog function input?
18.09.
`- Re: Is it illegal to use an (enum) as a Verilog function input?
16.09.
* Can anyone explain "cannot currently create a parameter of type" compilation err
18.09.
+- Re: Can anyone explain "cannot currently create a parameter of type" compilation err
17.09.
+* Re: Can anyone explain "cannot currently create a parameter of type" compilation err
17.09.
|`- Re: Can anyone explain "cannot currently create a parameter of type" compilation err
16.09.
`* Re: Can anyone explain "cannot currently create a parameter of type" compilation err
16.09.
 `- Re: Can anyone explain "cannot currently create a parameter of type" compilation err
16.09.
* Can a Verilog function take a boolean argument?
17.09.
`- Re: Can a Verilog function take a boolean argument?
15.09.
* Non-binary NCO Modulus
16.09.
`* Re: Non-binary NCO Modulus
16.09.
 +* Re: Non-binary NCO Modulus
16.09.
 |`- Re: Non-binary NCO Modulus
16.09.
 `* Re: Non-binary NCO Modulus
17.09.
  `* Re: Non-binary NCO Modulus
17.09.
   `* Re: Non-binary NCO Modulus
17.09.
    `* Re: Non-binary NCO Modulus
17.09.
     `- Re: Non-binary NCO Modulus
14.09.
* Gowin FPGA Oddities
15.09.
+* Re: Gowin FPGA Oddities
15.09.
|`- Re: Gowin FPGA Oddities
15.09.
+* Re: Gowin FPGA Oddities
15.09.
|`* Re: Gowin FPGA Oddities
15.09.
| `* Re: Gowin FPGA Oddities
15.09.
|  `* Re: Gowin FPGA Oddities
18.09.
|   +* Re: Gowin FPGA Oddities
18.09.
|   |`* Re: Gowin FPGA Oddities
18.09.
|   | +* Re: Gowin FPGA Oddities
18.09.
|   | |`- Re: Gowin FPGA Oddities
18.09.
|   | `* Re: Gowin FPGA Oddities
19.09.
|   |  `* Re: Gowin FPGA Oddities
20.09.
|   |   +- Re: Gowin FPGA Oddities
19.09.
|   |   `* Re: Gowin FPGA Oddities
20.09.
|   |    `- Re: Gowin FPGA Oddities
17.09.
|   `* Re: Gowin FPGA Oddities
17.09.
|    `* Re: Gowin FPGA Oddities
17.09.
|     `* Re: Gowin FPGA Oddities
17.09.
|      `* Re: Gowin FPGA Oddities
18.09.
|       `* Re: Gowin FPGA Oddities
18.09.
|        `* Re: Gowin FPGA Oddities
18.09.
|         `* Re: Gowin FPGA Oddities
18.09.
|          `- Re: Gowin FPGA Oddities
15.09.
`* Re: Gowin FPGA Oddities
15.09.
 +* Re: Gowin FPGA Oddities
15.09.
 |`- Re: Gowin FPGA Oddities
15.09.
 `- Re: Gowin FPGA Oddities
14.09.
* Trenz FPGA Module
14.09.
`* Re: Trenz FPGA Module
14.09.
 `* Re: Trenz FPGA Module
14.09.
  `* Re: Trenz FPGA Module
14.09.
   `* Re: Trenz FPGA Module
14.09.
    `- Re: Trenz FPGA Module
13.09.
* DE10 Standard Audio Demos not working
14.09.
`* Re: DE10 Standard Audio Demos not working
15.09.
 `* Re: DE10 Standard Audio Demos not working
15.09.
  `* Re: DE10 Standard Audio Demos not working
15.09.
   `* Re: DE10 Standard Audio Demos not working
15.09.
    `- Re: DE10 Standard Audio Demos not working
12.09.
* Active HDL and the Case of the Haunted Cursor
12.09.
`- Re: Active HDL and the Case of the Haunted Cursor
07.09.
* Go To VHDL Resource
08.09.
+- Re: Go To VHDL Resource
07.09.
`- Re: Go To VHDL Resource
03.09.
* What is a Processor and Software in Context of Reliability Analysis?
04.09.
`* Re: What is a Processor and Software in Context of Reliability Analysis?
04.09.
 `- Re: What is a Processor and Software in Context of Reliability Analysis?
30.08.
* ADCs in FPGAs
31.08.
+* Re: ADCs in FPGAs
31.08.
|`* Re: ADCs in FPGAs
03.09.
| `* Re: ADCs in FPGAs
03.09.
|  `- Re: ADCs in FPGAs
31.08.
+* Re: ADCs in FPGAs
31.08.
|`- Re: ADCs in FPGAs
31.08.
`- Re: ADCs in FPGAs
29.08.
* Are Gowin Serious Contenders?
04.09.
+- Re: Are Gowin Serious Contenders?
29.08.
`* Re: Are Gowin Serious Contenders?
29.08.
 `* Re: Are Gowin Serious Contenders?
29.08.
  `* Re: Are Gowin Serious Contenders?
04.09.
   +- Re: Are Gowin Serious Contenders?
30.08.
   +- Re: Are Gowin Serious Contenders?
29.08.
   `- Re: Are Gowin Serious Contenders?
25.08.
* iCE40 Ultra Family Data Sheet
27.08.
+* Re: iCE40 Ultra Family Data Sheet
27.08.
|`- Re: iCE40 Ultra Family Data Sheet
26.08.
`* Re: iCE40 Ultra Family Data Sheet
27.08.
 `* Re: iCE40 Ultra Family Data Sheet
28.08.
  `* Re: iCE40 Ultra Family Data Sheet
28.08.
   `* Re: iCE40 Ultra Family Data Sheet
28.08.
    `- Re: iCE40 Ultra Family Data Sheet
21.08.
* Potential New Design
24.08.
+* Re: Potential New Design
24.08.
|+* Re: Potential New Design
24.08.
||`* Re: Potential New Design
25.08.
|| `* Re: Potential New Design
24.08.
||  `- Re: Potential New Design
24.08.
|`- Re: Potential New Design
22.08.
+* Re: Potential New Design
22.08.
|`- Re: Potential New Design
22.08.
`* Re: Potential New Design
22.08.
 `* Re: Potential New Design
24.08.
  `- Re: Potential New Design
13.08.
o Re: Is FPGA code called firmware?
12.08.
o Elastic buffer implementation
09.08.
o VLSI SUBSCRIBE
08.08.
* Re: Some preliminary help for an FPGA selection
10.08.
`* Re: Some preliminary help for an FPGA selection
10.08.
 `* Re: Some preliminary help for an FPGA selection
10.08.
  `- Re: Some preliminary help for an FPGA selection
08.08.
o Some preliminary help for an FPGA selection
03.08.
* Entity-bound SDC file in Quartus Lite Edition?
03.08.
`- Re: Entity-bound SDC file in Quartus Lite Edition?
20.07.
o Re: Xilinx Xact Step Software
13.07.
o Re: Open source Verilog BCH encoder/decoder
10.07.
o Re: Need help finding Synario Futurenet 6.10
06.07.
o ICCD 2020: Call for Special Sessions and Tutorial Proposals
28.06.
* Lattice new 28nm series - any clues about availability ?
29.06.
+* Re: Lattice new 28nm series - any clues about availability ?
29.06.
|`* Re: Lattice new 28nm series - any clues about availability ?
29.06.
| `- Re: Lattice new 28nm series - any clues about availability ?
29.06.
`* Re: Lattice new 28nm series - any clues about availability ?
29.06.
 `* Re: Lattice new 28nm series - any clues about availability ?
29.06.
  `* Re: Lattice new 28nm series - any clues about availability ?
30.06.
   `* Re: Lattice new 28nm series - any clues about availability ?
30.06.
    `- Re: Lattice new 28nm series - any clues about availability ?
22.06.
o Reverse Engineering the Comtech AHA363 PCIe Gzip Accelerator Board
20.06.
* <whine mode on> Why is my source buried in the bowels of the project?
28.06.
+- Re: <whine mode on> Why is my source buried in the bowels of the project?
26.06.
+* Re: <whine mode on> Why is my source buried in the bowels of the project?
26.06.
|`- Re: <whine mode on> Why is my source buried in the bowels of the project?
23.06.
+- Re: <whine mode on> Why is my source buried in the bowels of the project?
23.06.
`- Re: <whine mode on> Why is my source buried in the bowels of the project?
16.06.
* Driving crystal with cheap FPGA ( MAchXO2) directly ?
28.06.
+* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
28.06.
|`* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
| +* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
| |`* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
02.07.
| | `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
02.07.
| |  `- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
28.06.
| `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
|  `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
|   +* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
|   |`* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
02.07.
|   | `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
02.07.
|   |  `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
03.07.
|   |   +- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
03.07.
|   |   `- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
|   +- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
|   `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
29.06.
|    `- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
22.06.
+* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
22.06.
|`* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
24.06.
| `- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
16.06.
`* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
16.06.
 `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
16.06.
  `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
16.06.
   +* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
16.06.
   |`* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
16.06.
   | `- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
16.06.
   `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
28.06.
    `* Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
28.06.
     `- Re: Driving crystal with cheap FPGA ( MAchXO2) directly ?
13.06.
* Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
16.06.
+* Re: Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
23.06.
|`- Re: Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
13.06.
`* Re: Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
14.06.
 `* Re: Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
14.06.
  `* Re: Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
14.06.
   `- Re: Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
05.06.
* enum and Vivado
05.06.
+* Re: enum and Vivado
05.06.
|`- Re: enum and Vivado
05.06.
+* Re: enum and Vivado
05.06.
|`* Re: enum and Vivado
05.06.
| `* Re: enum and Vivado
06.06.
|  `- Re: enum and Vivado
05.06.
`- Re: enum and Vivado
15.05.
* Looking for MMI M2018 LCA data sheet
17.05.
+- Re: Looking for MMI M2018 LCA data sheet
15.05.
`* Re: Looking for MMI M2018 LCA data sheet
15.05.
 `* Re: Looking for MMI M2018 LCA data sheet
15.05.
  +* Re: Looking for MMI M2018 LCA data sheet
15.05.
  |`* Re: Looking for MMI M2018 LCA data sheet
15.05.
  | `* Re: Looking for MMI M2018 LCA data sheet
15.05.
  |  +* Re: Looking for MMI M2018 LCA data sheet
15.05.
  |  |`* Re: Looking for MMI M2018 LCA data sheet
16.05.
  |  | `* Re: Looking for MMI M2018 LCA data sheet
16.05.
  |  |  `- Re: Looking for MMI M2018 LCA data sheet
15.05.
  |  `* Re: Looking for MMI M2018 LCA data sheet
15.05.
  |   `* Re: Looking for MMI M2018 LCA data sheet
15.05.
  |    `* Re: Looking for MMI M2018 LCA data sheet
22.05.
  |     `- Re: Looking for MMI M2018 LCA data sheet
15.05.
  `- Re: Looking for MMI M2018 LCA data sheet
06.05.
* fixed point modeling tools
07.05.
`* Re: fixed point modeling tools
07.05.
 `* Re: fixed point modeling tools
08.05.
  `* Re: fixed point modeling tools
08.05.
   `- Re: fixed point modeling tools
05.05.
* Passing digitized data to design
06.05.
`* Re: Passing digitized data to design
06.05.
 `* Re: Passing digitized data to design
06.05.
  `* Re: Passing digitized data to design
06.05.
   `* Re: Passing digitized data to design
06.05.
    `- Re: Passing digitized data to design
17.04.
* Re: Custom CPU Designs
17.04.
`* Re: Custom CPU Designs
17.04.
 `* Re: Custom CPU Designs
17.04.
  `- Re: Custom CPU Designs
17.04.
o CFP IEEE International Conference on Computer Design (ICCD) 2020
16.04.
* CPU Softcore Compendium
16.04.
`* Re: CPU Softcore Compendium
28.06.
 `* Re: CPU Softcore Compendium
30.06.
  `* Re: CPU Softcore Compendium
05.07.
   `- Re: CPU Softcore Compendium
06.04.
* Terminated
08.04.
`* Re: Terminated
09.04.
 `- Re: Terminated
02.04.
* No more gate-level simulation. for Cyclone V !!!
03.04.
`* Re: No more gate-level simulation. for Cyclone V !!!
03.04.
 +* Re: No more gate-level simulation. for Cyclone V !!!
15.04.
 |+* Re: No more gate-level simulation. for Cyclone V !!!
15.04.
 ||`* Re: No more gate-level simulation. for Cyclone V !!!
16.04.
 || `- Re: No more gate-level simulation. for Cyclone V !!!
03.04.
 |`* Re: No more gate-level simulation. for Cyclone V !!!
04.04.
 | `- Re: No more gate-level simulation. for Cyclone V !!!
03.04.
 `- Re: No more gate-level simulation. for Cyclone V !!!
24.03.
* Use example of Intel University program in Intel Quartus - problem with Board su
24.03.
`* Re: Use example of Intel University program in Intel Quartus - problem with Board su
25.03.
 +* Re: Use example of Intel University program in Intel Quartus - problem with Board su
25.03.
 |`- Re: Use example of Intel University program in Intel Quartus - problem with Board su
24.03.
 `- Re: Use example of Intel University program in Intel Quartus - problem with Board su
21.03.
* PipelineC - C-like almost hardware description language - AWS F1 Example
22.03.
`* Re: PipelineC - C-like almost hardware description language - AWS F1 Example
23.03.
 `- Re: PipelineC - C-like almost hardware description language - AWS F1 Example
19.03.
o Using EDA tools at home
18.02.
* Re: Is FPGA code called firmware?
22.02.
`- Re: Is FPGA code called firmware?
13.02.
* How to generate bits info for a record structure?
13.02.
`* How to generate bits info for a record structure?
13.02.
 `* Re: How to generate bits info for a record structure?
14.02.
  +* Re: How to generate bits info for a record structure?
14.02.
  |`* Re: How to generate bits info for a record structure?
14.02.
  | `* Re: How to generate bits info for a record structure?
14.02.
  |  +- Re: How to generate bits info for a record structure?
14.02.
  |  `* Re: How to generate bits info for a record structure?
14.02.
  |   `- Re: How to generate bits info for a record structure?
13.02.
  `- Re: How to generate bits info for a record structure?
13.02.
* Code block in icestudio
13.02.
`* Re: Code block in icestudio
13.02.
 `* Re: Code block in icestudio
13.02.
  `* Re: Code block in icestudio
14.02.
   +* Re: Code block in icestudio
14.02.
   |`- Re: Code block in icestudio
13.02.
   `* Re: Code block in icestudio
14.02.
    `* Re: Code block in icestudio
14.02.
     `* Re: Code block in icestudio
17.02.
      `* Re: Code block in icestudio
18.02.
       `* Re: Code block in icestudio
19.02.
        +- Re: Code block in icestudio
18.02.
        `* Re: Code block in icestudio
20.02.
         +* Re: Code block in icestudio
21.02.
         |+- Re: Code block in icestudio
20.02.
         |`* Re: Code block in icestudio
20.02.
         | `- Re: Code block in icestudio
20.02.
         `- Re: Code block in icestudio
06.02.
* how to suppress assertion warnings in gtkwave?
06.02.
`* Re: how to suppress assertion warnings in gtkwave?
07.02.
 `* Re: how to suppress assertion warnings in gtkwave?
07.02.
  `- Re: how to suppress assertion warnings in gtkwave?
27.01.
* Re: Is FPGA code called firmware?
29.01.
`* Re: Is FPGA code called firmware?
30.01.
 +* Re: Is FPGA code called firmware?
29.01.
 |`* Re: Is FPGA code called firmware?
30.01.
 | `* Re: Is FPGA code called firmware?
30.01.
 |  +* Re: Is FPGA code called firmware?
31.01.
 |  |`* Re: Is FPGA code called firmware?
01.02.
 |  | +* Re: Is FPGA code called firmware?
02.02.
 |  | |`* Re: Is FPGA code called firmware?
02.02.
 |  | | `* Re: Is FPGA code called firmware?
04.02.
 |  | |  `* Re: Is FPGA code called firmware?
04.02.
 |  | |   `- Re: Is FPGA code called firmware?
31.01.
 |  | `* Re: Is FPGA code called firmware?
01.02.
 |  |  `- Re: Is FPGA code called firmware?
30.01.
 |  `- Re: Is FPGA code called firmware?
29.01.
 `* Re: Is FPGA code called firmware?
30.01.
  `* Re: Is FPGA code called firmware?
29.01.
   `* Re: Is FPGA code called firmware?
30.01.
    `* Re: Is FPGA code called firmware?
30.01.
     `- Re: Is FPGA code called firmware?
21.01.
o Add Hunter
13.01.
o Apple eBook on Educational CPU design using FPGA
07.01.
* Displays - Apple Mac vs. IBM PC
08.01.
`* Re: Displays - Apple Mac vs. IBM PC
08.01.
 `* Re: Displays - Apple Mac vs. IBM PC
08.01.
  +* Re: Displays - Apple Mac vs. IBM PC
10.01.
  |`* Re: Displays - Apple Mac vs. IBM PC
11.01.
  | `* Re: Displays - Apple Mac vs. IBM PC
12.01.
  |  `- Re: Displays - Apple Mac vs. IBM PC
08.01.
  +* Re: Displays - Apple Mac vs. IBM PC
08.01.
  |`- Re: Displays - Apple Mac vs. IBM PC
08.01.
  `* Re: Displays - Apple Mac vs. IBM PC
09.01.
   `- Re: Displays - Apple Mac vs. IBM PC
04.01.
* Optimizations, How Much and When?
05.01.
+* Re: Optimizations, How Much and When?
05.01.
|`* Re: Optimizations, How Much and When?
05.01.
| `* Re: Optimizations, How Much and When?
05.01.
|  +* Re: Optimizations, How Much and When?
06.01.
|  |`- Re: Optimizations, How Much and When?
05.01.
|  `* Re: Optimizations, How Much and When?
06.01.
|   `- Re: Optimizations, How Much and When?
05.01.
`* Re: Optimizations, How Much and When?
05.01.
 `* Re: Optimizations, How Much and When?
06.01.
  `* Re: Optimizations, How Much and When?
06.01.
   `- Re: Optimizations, How Much and When?
05.12.
* Enabler for New FPGA Companies
05.12.
`* Re: Enabler for New FPGA Companies
06.12.
 `- Re: Enabler for New FPGA Companies
04.12.
* Anybody used Amazon AWS for HW sims?
05.12.
`* Re: Anybody used Amazon AWS for HW sims?
05.12.
 `* Re: Anybody used Amazon AWS for HW sims?
05.12.
  `* Re: Anybody used Amazon AWS for HW sims?
05.12.
   `- Re: Anybody used Amazon AWS for HW sims?
03.12.
o Issue regarding boot qspi flash in zynq
29.11.
* tell me what you think!
29.11.
`- Re: tell me what you think!
29.11.
* SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not work ?
29.11.
`* Re: SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not work ?
29.11.
 `- Re: SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not work ?
28.11.
* Lattice's ECP5 - half of the program went MIA - WTF ?
29.11.
+- Re: Lattice's ECP5 - half of the program went MIA - WTF ?
29.11.
`* Re: Lattice's ECP5 - half of the program went MIA - WTF ?
29.11.
 `* Re: Lattice's ECP5 - half of the program went MIA - WTF ?
30.11.
  `* Re: Lattice's ECP5 - half of the program went MIA - WTF ?
30.11.
   `* Re: Lattice's ECP5 - half of the program went MIA - WTF ?
30.11.
    `- Re: Lattice's ECP5 - half of the program went MIA - WTF ?
28.11.
* Efinix and their new Trion FPGAs -
12.12.
+* Re: Efinix and their new Trion FPGAs -
12.12.
|`- Re: Efinix and their new Trion FPGAs -
03.12.
+* Re: Efinix and their new Trion FPGAs -
04.12.
|`* Re: Efinix and their new Trion FPGAs -
05.12.
| `* Re: Efinix and their new Trion FPGAs -
05.12.
|  `* Re: Efinix and their new Trion FPGAs -
11.12.
|   `- Re: Efinix and their new Trion FPGAs -
29.11.
`* Re: Efinix and their new Trion FPGAs -
29.11.
 `* Re: Efinix and their new Trion FPGAs -
29.11.
  `- Re: Efinix and their new Trion FPGAs -
28.11.
* Efinix and their Trion FPGAs
29.11.
`* Re: Efinix and their Trion FPGAs
29.11.
 `- Re: Efinix and their Trion FPGAs
25.11.
* New coding method for a state machine in groups in HDL
27.11.
+* Re: New coding method for a state machine in groups in HDL
27.11.
|`* Re: New coding method for a state machine in groups in HDL
27.11.
| `* Re: New coding method for a state machine in groups in HDL
27.11.
|  `* Re: New coding method for a state machine in groups in HDL
28.11.
|   `* Re: New coding method for a state machine in groups in HDL
28.11.
|    `* Re: New coding method for a state machine in groups in HDL
29.11.
|     `* Re: New coding method for a state machine in groups in HDL
29.11.
|      `* Re: New coding method for a state machine in groups in HDL
30.11.
|       +- Re: New coding method for a state machine in groups in HDL
30.11.
|       `* Re: New coding method for a state machine in groups in HDL
30.11.
|        +* Re: New coding method for a state machine in groups in HDL
30.11.
|        |`* Re: New coding method for a state machine in groups in HDL
30.11.
|        | `* Re: New coding method for a state machine in groups in HDL
30.11.
|        |  `- Re: New coding method for a state machine in groups in HDL
30.11.
|        `* Re: New coding method for a state machine in groups in HDL
30.11.
|         `* Re: New coding method for a state machine in groups in HDL
02.12.
|          `* Re: New coding method for a state machine in groups in HDL
03.12.
|           `- Re: New coding method for a state machine in groups in HDL
26.11.
+- Re: New coding method for a state machine in groups in HDL
26.11.
+- Re: New coding method for a state machine in groups in HDL
26.11.
`* Re: New coding method for a state machine in groups in HDL
26.11.
 `* Re: New coding method for a state machine in groups in HDL
26.11.
  `* Re: New coding method for a state machine in groups in HDL
27.11.
   +- Re: New coding method for a state machine in groups in HDL
26.11.
   `* Re: New coding method for a state machine in groups in HDL
27.11.
    +- Re: New coding method for a state machine in groups in HDL
26.11.
    `* Re: New coding method for a state machine in groups in HDL
27.11.
     `* Re: New coding method for a state machine in groups in HDL
27.11.
      `* Re: New coding method for a state machine in groups in HDL
27.11.
       `* Re: New coding method for a state machine in groups in HDL
27.11.
        `- Re: New coding method for a state machine in groups in HDL
16.11.
* AGM vs. Gowin
24.11.
+* Re: AGM vs. Gowin
24.11.
|`- Re: AGM vs. Gowin
24.11.
`- Re: AGM vs. Gowin
15.11.
* AGM AG6K SoC
16.11.
`* Re: AGM AG6K SoC
16.11.
 `- Re: AGM AG6K SoC
13.11.
* Gowin Semiconductor, Real or Fake?
14.11.
+* Re: Gowin Semiconductor, Real or Fake?
14.11.
|`- Re: Gowin Semiconductor, Real or Fake?
14.11.
+* Re: Gowin Semiconductor, Real or Fake?
14.11.
|`- Re: Gowin Semiconductor, Real or Fake?
13.11.
+- Re: Gowin Semiconductor, Real or Fake?
13.11.
`- Re: Gowin Semiconductor, Real or Fake?
08.11.
* FPGA config sizes
10.11.
+- Re: FPGA config sizes
09.11.
+* Re: FPGA config sizes
09.11.
|`* Re: FPGA config sizes
09.11.
| `- Re: FPGA config sizes
08.11.
+- Re: FPGA config sizes
08.11.
+- Re: FPGA config sizes
08.11.
+- Re: FPGA config sizes
08.11.
`* Re: FPGA config sizes
08.11.
 `* Re: FPGA config sizes
11.11.
  `* Re: FPGA config sizes
11.11.
   `* Re: FPGA config sizes
11.11.
    `* Re: FPGA config sizes
11.11.
     `- Re: FPGA config sizes
07.11.
* Re: Lattice XO3D New
07.11.
`* Re: Lattice XO3D New
11.11.
 `* Re: Lattice XO3D New
12.11.
  `* Re: Lattice XO3D New
12.11.
   +* Re: Lattice XO3D New
13.11.
   |`- Re: Lattice XO3D New
12.11.
   `- Re: Lattice XO3D New
07.11.
* Lattice MachXO2/XO3/XO3D vs ECP5
07.11.
+* Re: Lattice MachXO2/XO3/XO3D vs ECP5
16.11.
|`- Re: Lattice MachXO2/XO3/XO3D vs ECP5
07.11.
`- Re: Lattice MachXO2/XO3/XO3D vs ECP5
08.10.
* Re: Tiny CPUs for Slow Logic
08.10.
`* Re: Tiny CPUs for Slow Logic
16.10.
 `* Re: Tiny CPUs for Slow Logic
25.10.
  `* EDIF as machine language
25.10.
   +* Re: EDIF as machine language
25.10.
   |`- Re: EDIF as machine language
25.10.
   `* Re: EDIF as machine language
25.10.
    `* Re: EDIF as machine language
25.10.
     `* Re: EDIF as machine language
25.10.
      `- Re: EDIF as machine language

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